場域應用與服務設計
with Claude
Monday, December 01, 2025
RF IC Design Optimization
RF IC
cf:
Apple C1 Transceiver Architecture
3.5 GHz LNA
N7
,
N16
,
share
,
slides
,
Smith Chart
in Optimizer,
Smith Chart
,
GD/(A*) and R.C.
slides,
schematic
0.6 – 6 GHz (Sub-6),
slides
,
slides+
LNA Cadence files (slides)
approximation
,
Spice vs Spectre PSS
slides
,
PSS on LNA
slides
Optimized vs. Original
(5 GHz),
Reality check
(slides)
schematic
how to get this
running ngspice in Claude VM (
amazing story
)
initial parameters (
MNA
)
optimized parameters (
share
)
Build Sub 6 GHz Power Amplifier Optimizer with Die Synced
Prompts
,
artifact
Load-Pull Contours
9.0 GHz PLL
,
share
,
NM Version
Apple C1 ADPLL — 7.0 GHz
(
spec
),
NM Version
,
NM Algo
Apple C1 ADPLL — 7.0 GHz
閱讀:
AI 在IC設計的應用
Cadence AI-Powered Design Solutions
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