場域應用與服務設計

Tuesday, November 03, 2026

HW#8

課堂練習

Deadline: Saturday at 23:59 (one more week)

Send all the share links to me chang212@gmail.com by email with subject HW#8 [your id, your name]

What you can do to prevent accidents:

模擬一個意外事件，然後模擬一個預防措施

範例

Photos: photo gallery.

Sunday, October 25, 2026

Voronoi-based Robot Navigation

artifact (Credit: Lisa)

Theme park (credit Black Hunter)

Voronoi navigation, share

Motor Works (Credit: Lisa)

HW#7 Voromoi-based Navigation

課堂練習

Deadline: Saturday at 23:59 (one more week)

Send all the share links to me chang212@gmail.com by email with subject HW#7 [your id, your name]

1. 設計一個能閃避靜止障礙物的3D Voronoi尋徑系統（以下場景可擇一，或使用有版權的照片）

（加分題，可不做）2. 設計一個能閃避行人與靜止障礙物的機器人導引系統，系統必須經過以下真實情境的壓力測試。

行人移動模式 SocNavBench 2021 source https://arxiv.org/pdf/2103.00047

3. Design a 3D Voronoi Navigation (機器人取瓶中物，太空船穿越隕石帶，機器臂組裝汽車...)

Hint: 3d Voronoi

參考界面

Monday, October 19, 2026

HW#6 3D Navigation

課堂練習

Deadline: Saturday at 23:59 (one more week)

Send all the share links to me chang212@gmail.com by email with subject HW#6 [your id, your name]

第一題與第二題是二選一即可

第三題必做

製作以下場景的3D導航，然後完成以下二個任務

artifact (share) *non-Voronoi

task 1: make an entrance/exit. make the auto-navigation route deliberately exit through this gate (e.g., a waypoint placed just outside on the brick path) and go to central woods as destination.

task 2: set FPV (first-person view) and maintain horizontal view angle

2. 設計一個能閃避靜止障礙物的3D尋徑系統（以下場景可擇一）

參考介面

3. 設計一個具有導航安全性的行走機器人，首先建立一個公共場所（公園，校園，百貨公司，圖書館...)，然後進行以下三個設計

a. 如何有效增加機器人與行人的最小距離（淨距離）？

b. 給予完整地圖或建構視線內地圖何者可以增加淨距離？

c. 如果機器人每一刻都知道場上所有行人的位置，對增加淨距離有幫助嗎? 如果有，量化幫助有多少？

Tuesday, October 13, 2026

HW#5 P&R for OP 741.

課堂練習

Deadline: This Saturday at 23:59

Send all the share links to me chang212@gmail.com by email with your subject line to show HW#5 [your id, your name]

P&R for OP 741.

schematic

「用 Claude 做類比 IC 設計」系列頁面12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19模型：NPN β 200、V_A 100 V；橫向 PNP β 50、V_A 50 V、τ_F 30 ns；V_T 25.85 mV、V_BE 0.65 V回到部落格文章

Handout: Analog IC Design (OP741, diff pair, Placement & Routing)

Place and route the IC OP741

Layout targets

These targets apply only to the bonus phases. They are measured on the extended netlist from Phase 2 and averaged over the same 10 seeds. Phase 1 is graded on reproduction and ablation alone. "Phase 1 baseline" means your own reproduction of the handout on that netlist before any change.

Metric	Target	Handout baseline
Routing convergence	10/10 seeds with 0 shared cells	10/10 (core only)
PathFinder rounds	mean ≤ 4	2–4
Input path-length match	mean ≥ 95%, worst seed ≥ 90%	95.0% (seed 137)
Input-net resistance mismatch, vias included	≤ 2%	—
Coupling, each input net to VOUT	≤ 2 fF, and Vin+ within 10% of Vin−	—
Output-stage centroid	within 1 cell of x = 40	—
Output stage to input quad	≥ 40% of die height apart	—
Thermal offset estimate (2 °C/mm model)	≤ 50 µV	—
Wirelength + vias	≤ 1.15× Phase 1 baseline	434 + 24 (seed 137)
Runtime per seed	≤ 2× Phase 1 baseline	—

A team that misses a target but explains the trade-off with data can still earn most of the credit.

Project tasks

Run the handout's engine on the single-stage diff pair and the two-stage core. Reproduce every row of the handout's Table 1 and the two-stage result.
Remove one part at a time and measure the effect on convergence, rounds, match, wirelength and vias:
- SimPL-style anchors off
- RUDY congestion stage off (λ = 0)
- halo m = 0, 1 and 2
- nets routed as trees vs split into two-pin connections
- one layer vs three layers
Record runtime per seed. This is the Phase 1 baseline used in the targets.

Checkpoint: a reproduction table next to the handout's numbers, plus one ablation table. Explain any number that differs from the handout by more than 10%.