RF IC Design Optimization

LNA

cf: Apple C1 Transceiver Architecture 

3.5 GHz LNA N7 (closed-form), N16,  share, slides,  Smith Chart in Optimizer, Smith Chart, Optimizer UI with synced sliders (closed-form), MNA Optimizer on Die 

schematic 0.6 – 6 GHz (Sub-6),slides, slides+

Optimized vs. Original (5 GHz), md, Reality check (slides), md

schematic

how to get this

running ngspice in Claude VM (findings, ill., also Cadence below, handout md)

initial parameters running MNA (findings, ill., handout md, detail md)

optimized parameters using MNA (share, handout md)

Use Cowork

analytical vs. MNA

auto-correction of model, auto-optimize parameters

until all specs pass

Cadence

Cadence files (slides) LNA approximation, Spice vs Spectre PSS slides, PSS on LNA slides

AI-Assisted Workflow Speedup

AI 在IC設計的應用 Cadence AI-Powered Design Solutions

Design Space Optimization

PA Sub 6 GHz

Load-Pull Contours

Build Sub 6 GHz Power Amplifier Optimizer with Die Synced

Prompts, artifact (Closed-Form), artifact (MNA)

PLL (Phase-Locked Loop)

Importance of PLL

9.0 GHz PLL, share, NM Version (Analytical), schematic

Apple C1 ADPLL — 7.0 GHz (spec), NM Version, NM cross checked by MNA, NM Algo (Analytical) Optimizer with trajectory (MNA), share, schematic

Apple C1 ADPLL — 7.0 GHz  (C1 is N4P)